1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a semiconductor device having shallow and deep source/drain regions.
2. Description of the Related Art
The source/drain regions of recently developed high-density semiconductor devices have a lightly doped drain (LDD) structure to suppress short channel effects. The source/drain regions, that comprise an LDD structure, include a low-density, shallow source/drain region on a semiconductor substrate adjacent to a gate pattern and a deep source/drain region on the semiconductor substrate adjacent to the shallow source/drain region. The shallow source/drain region is referred to as a source/drain extension because it extends from the deep source/drain region.
However, as the line width of the gate patterns of semiconductor devices becomes 90 nm or less, shallow source/drain regions having shallower junctions and lower resistances are needed. High-energy ion-implantation and annealing (a thermal process) for activating the ion-implanted impurities are used to form the deep source/drain region. The annealing process diffuses the ion-implanted impurities. Therefore, it is difficult to form a shallow source/drain region having a shallow junction and a low resistance.
A reverse-ordered source/drain region formation method has been introduced in an attempt to solve such an impediment to the forming of both a deep source/drain region and a shallow source/drain region having a shallow junction and low resistance. According to the reverse-ordered source/drain region formation method, the shallow source/drain region (source/drain extension) is formed after the deep source/drain region is formed. More specifically, a disposable spacer is formed at both sidewalls of a gate pattern. The structure is then subjected to ion-implantation and a thermal treatment to form the deep source/drain region. Then the disposable spacer is removed. The resultant structure is then ion-implanted and thermally treated, thus forming the shallow source/drain region. However, according to the reverse-ordered source/drain region formation method, the ion-implanted impurities overlap each other in the shallow source/drain region due to the small line width of the gate pattern.
An offset spacer formation method has been suggested as a way to solve such a problem. According to the offset spacer formation method, a first spacer is formed before the shallow source/drain region is formed. Then the ion-implantation process and thermal process are performed to prevent the ion-implanted impurities from overlapping. After the shallow source/drain region is formed, a second spacer is formed. The resultant structure is subjected to ion-implantation, and a thermal treatment.
However, the offset spacer formation method causes direct etch damage to the active region when the first and second spacers are formed. If the second spacer is formed without removing the first spacer, it is difficult to form the second spacer to an appropriate thickness between adjacent gates by using conventional deposition and etching techniques, due to the high density of the device. Removing the second spacer causes etch damage to the active region. Even worse, according to the offset spacer formation method, at least four films are deposited to form the two spacers, which results in a large thermal budget for the semiconductor device.